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Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/23509

Title: SoC/FPGA Architecture for High-Speed Low-Latency Blob Detection
Authors: Yu, Zhengqiang
Claesen, Luc
Pan, Yun
Motten, Andy
Wang, Yimu
Yan, Xiaolang
Issue Date: 2013
Publisher: STW
Citation: Proceedings ICT.OPEN 2013, STW,
Abstract: Image processing is usually divided up in a number of processing stages. In the preprocessing stage, basic image processing algorithms such as convolution operations, Gausian filtering, edge detection, tresholding, histogram calculation etc. is being performed. In a second stage, selected image areas indicating the objects of interest have to be identified and labeled with a unique label for each connected component. Such connectded components are also called “blobs”. This paper presents a high-speed real-time blob detection- and labeling system as implemented on an FPGA architecture. The architecture has been developed in a parametrized way enabling it to be used in various real-time image processing applications. Most software implementations for blob detection make use of two passes through each image frame. This requires too much processing and memory overhead. Two passes over the frame buffer also results a large latency of several milliseconds, which is unacceptable in many applications. In this paper, a one-pass architecture for FPGA implementation is presented. Besides the advantage of only requiring on-chip block RAM and no external frame buffer, it has the aditional advantage of very short latency. The latency is only a few line periods instead of video frames. The fram time is usually three orders of magnitude larger than a line period. The system has been implemented on an Altera Cyclone-II FPGA and has been demonstrated by a real-time 1000 frames/sec blob detection system as can be used in high responsive ir-light based human computer interaction. To enable an efficient hardware implementation a run-length encoding of the binary input video stream is used together with a dedicated memory architecture for labeling and updating the labeling whereby only the information of two lines needs to be stored in FPGA on-chip block RAM.
URI: http://hdl.handle.net/1942/23509
Link to publication: http://www.ictopen2013.nl/content/proceedings+2013
ISBN: 9789073461840
Category: C1
Type: Proceedings Paper
Appears in Collections: Research publications

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