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Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/23120

Title: SoC Oriented Real-time High-quality Stereo Vision System
Authors: Li, Yanzhe
Huang, Kai
Claesen, Luc
Issue Date: 2016
Publisher: IEEE Xplore
Citation: 2016 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), IEEE Xplore,
Series/Report: IEEE Xplore
Abstract: Stereo matching is a crucial step to extract depth information from stereo images. However, it is still challenging to achieve good performance in both speed and accuracy for various stereo vision applications. In this paper, a hardware-compatible stereo matching algorithm is proposed and its associated hardware implementation is also presented. The proposed algorithm can produce high-quality disparity maps with the combined use of the mini-census transform, segmentation-based adaptive support weight and effective refinement. Moreover, the proposed architecture is optimized as a fully pipelined and scalable hardware system. Implemented on an Altera Stratix-IV FPGA board, it can achieve 65 frames per second (fps) for 1024 × 768 stereo images and a 64 pixel disparity range. The proposed architecture is evaluated based on the Middlebury benchmarks and the average error rate is 6.56%. The experimental results indicate that the accuracy is competitive with some state-of-the-art software implementations.
Notes: Li, YZ (reprint author), Zhejiang Univ, Inst VLSI Design, Hangzhou, Zhejiang, Peoples R China. liyz@vlsi.zju.edu.cn; huangk@vlsi.zju.edu.cn; luc.claesen@uhasselt.be
URI: http://hdl.handle.net/1942/23120
DOI: 10.1109/VLSI-SoC.2016.7753558
ISI #: 000391865200024
ISBN: 9781509035618
ISSN: 2324-8440
Category: C1
Type: Proceedings Paper
Validation: ecoom, 2018
Appears in Collections: Research publications

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