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Please use this identifier to cite or link to this item: http://hdl.handle.net/1942/11692

Title: An On-Chip Parallel Memory Architecture for a Stereo-Vision System
Authors: MOTTEN, Andy
Issue Date: 2010
Publisher: IEEE
Citation: Proceedings of the 17th IEEE ICECS 2010. p. 500-503.
Abstract: This paper present a novel parallel System-on-Chip(SoC) memory architecture for a stereo vision system as required in 3D TV applications. It allows for a parallel access to all pixels located in a chosen window of the image. Using this architecture a complete window refresh on each clock cycle is possible, which can be used to increase the depth range of a stereo vision algorithm. This architecture is fully scalable and parameterizable to allow for custom SoC implementations as well as rapid phototyping on FPGAs. Hardware resource utilization for different processor window size configurations is compared based on FPGA logic element use.
URI: http://hdl.handle.net/1942/11692
ISBN: 978-1-4244-8156-9
Category: C1
Type: Proceedings Paper
Appears in Collections: Research publications

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